1. Field of the Invention
The present invention relates to semiconductor device manufacturing apparatuses and control methods thereof. In particular, the invention relates to a semiconductor device manufacturing apparatus and a control method thereof which enable an efficient transportation of a process lot consisting of semiconductor wafers to be processed.
2. Description of the Background Art
Semiconductor devices such as a semiconductor memory device as a representative one have conventionally been manufactured through process steps in which the surface of a semiconductor wafer is subjected to various treatments such as film deposition and etching. A manufacturing apparatus for the semiconductor devices is thus constituted of various equipment and units such as a processing apparatus for film deposition and transfer equipment for transporting a semiconductor wafer as described below.
FIG. 17 is a perspective view showing a processing apparatus employed in a semiconductor device manufacturing apparatus for processing a semiconductor wafer. The processing apparatus is now described in conjunction with FIG. 17.
Referring to FIG. 17, processing apparatus 104 includes load ports 105a and 105b, load lock chambers 106a and 106b, a wafer transfer unit 107, a pretreatment chamber 108, and a posttreatment chamber 109. Load lock chambers 106a and 106b are located adjacently to respective load ports 105a and 105b. Pretreatment chamber 108 and posttreatment chamber 109 are located opposite to load lock chambers 106a and 106b with wafer transfer unit 107 therebetween.
Load ports 105a and 105b receive, from the outside of processing apparatus 104, a semiconductor wafer cassette 102 holding a process lot (or lot) consisting of semiconductor wafers 101 to be processed. The lot constituted of semiconductor wafers 101 which is housed in semiconductor wafer cassette 102 is handled as a unit for managing fabrication of a semiconductor device at semiconductor wafer 101.
An operation of processing apparatus 104 is described starting with transport of semiconductor wafer cassette 102 to load port 105b for briefly explaining the operation. A lot consisting of semiconductor wafers 101 is drawn out of semiconductor wafer cassette 102 transported to load port 105b. The lot thus drawn out is held in load lock chamber 106b. The air within load lock chamber 106b is then discharged for processing the semiconductor wafers in a vacuum. The inside of load lock chamber 106b is kept in the vacuum state. Semiconductor wafers 101 in vacuum load lock chamber 106b are taken out one by one and fed into pretreatment chamber 108 by wafer transfer unit 107. In pretreatment chamber 108, semiconductor wafer 101 undergoes first processing. After the first processing in pretreatment chamber 108, semiconductor wafer 101 is transported by wafer transfer unit 107 from pretreatment chamber 108 to posttreatment chamber 109 for undergoing second processing. In posttreatment chamber 109, semiconductor wafer 101 is subjected to the second processing. Semiconductor wafer 101 which has undergone the second processing is returned by wafer transfer unit 107 to load lock chamber 106b. These process steps are successively performed for semiconductor wafers 101 held in load lock chamber 106b which have not been processed. In other words, immediately after a preceding semiconductor wafer 101 which has been processed in pretreatment chamber 108 is transported to posttreatment chamber 109, another semiconductor wafer 101 in load lock chamber 106b is fed into pretreatment chamber 108. In this way, all semiconductor wafers 101 of the lot held in load lock chamber 106b are processed and then transported back to load lock chamber 106b. Air is then supplied into load lock chamber 106b to return it into atmospheric state. After this, the lot consisting of processed semiconductor wafers 101 (processed lot) is transferred from load lock chamber 106b into the original semiconductor wafer cassette 102 held at load port 105b and stored therein. Semiconductor wafer cassette 102 holding the processed lot is transferred from load port 105b to the outside of processing apparatus 104. A series of process steps in processing apparatus 104 for the semiconductor wafers is accordingly completed.
Processing apparatus 104 shown in FIG. 17 has two load ports 105a and 105b and two load lock chambers 106a and 106b placed therein. When a lot constituted of semiconductor wafers 101 currently being processed exists in one load lock chamber 106b, a lot consisting of semiconductor wafers to be processed next (next-processed lot) can be received in the other load lock chamber 106a via load port 105a and wait there. Accordingly, semiconductor wafers 101 can be processed consecutively in pretreatment chamber 108 and posttreatment chamber 109.
FIG. 18 shows an entire structure of the semiconductor device manufacturing apparatus. The semiconductor device manufacturing apparatus has a plurality of bays 172. Bays 172 each treated as a unit for management include a plurality of processing apparatuses 104 as shown in FIG. 17, a stocker 115 containing a semiconductor wafer cassette which houses a lot consisting of semiconductor wafers to be processed in processing apparatuses 104, and an intra-bay transfer apparatus 110 for transferring the semiconductor wafer cassette between stocker 115 and processing apparatus 104 and between processing apparatuses 104. Bays 172 are connected by an inter-bay transfer apparatus 123 which can transport the semiconductor wafer cassette between bays 172. Processing apparatuses 104 include various processing apparatuses such as film deposition equipment and etching equipment for manufacturing a semiconductor device. In a predetermined manufacturing process of the semiconductor device, a semiconductor wafer cassette holding a lot consisting of semiconductor wafers to be processed is transported to predetermined processing apparatuses successively through predetermined process steps for performing predetermined processing on the semiconductor wafers.
Production of a semiconductor device thus requires that a lot consisting of semiconductor wafers to be processed is efficiently transported to various processing apparatuses. A conventional control process employed for transporting such a lot (i.e. a semiconductor wafer cassette holding a lot) is shown in FIG. 19. FIG. 19 shows a flow chart illustrating a lot transfer process in a conventional semiconductor device manufacturing apparatus. This process is controlled by a controller for controlling loading and unloading of a lot to and from processing apparatuses 104. The controller controls processing apparatuses 104; intra-bay transfer apparatus 110 and stocker 115 constituting bay 172 and inter-bay transfer apparatus 123. Details of the process are described in conjunction with FIG. 19.
Referring to FIG. 19, the process starts for each predetermined event (step 131). After the process starts, a dispatch process (step 132) is performed for determining a lot to be processed next (next-processed lot) in processing apparatus 104 being controlled. Simultaneously with the dispatch process (step 132), a retrieve process (step 133) is performed for determining a destination of a lot which has been processed (processed lot) in processing apparatus 104. Subsequently, a transfer execution process (step 134) is conducted. In the transfer execution process (step 134), the next-processed lot which is designated in the dispatch process (step 132) is sent to a load port of the processing apparatus 104, or the processed lot is sent to the determined destination from the load port of the processing apparatus 104. After the transfer process, the process shown in FIG. 19 is completed (step 135). It is noted that no transfer occurs in the transfer execution process (step 134) if the next-processed lot and the destination of the processed lot are not determined in the dispatch process (step 132) and the retrieve process (step 133) respectively.
After the lot transfer process shown in FIG. 19, the next-processed lot is fed to any of load ports 105a and 105b (see FIG. 17) which is vacant in processing apparatus 104. The controller of the semiconductor device manufacturing apparatus then starts a different process in order to start processing of semiconductor wafer 101 in processing apparatus 104. If the processed lot is transported from processing apparatus 104 to stocker 115, for example, the controller performs another process in order to allow the processed lot to be sent to another processing apparatus 104 in bay 172 or a processing apparatus 104 in another bay 172 and undergo next processing therein.
The process shown in FIG. 19 is described below in more detail. FIG. 20 shows a flow chart illustrating details of the dispatch process (step 132) in FIG. 19. The dispatch process is described in conjunction with FIG. 20.
Referring to FIG. 20, the dispatch process (step 132) starts (step 136) to perform a load port vacancy detecting process (step 137) for detecting whether load ports 105a and 105b in any processing apparatus 104 are vacant. If vacancy of load port 105a or 105b is detected, a search is conducted for a lot among lots held in stocker 115 that can be processed in processing apparatus 104. If there are a plurality of lots which can be processed, a lot to be processed next (next-processed lot) in the processing apparatus is determined based on predetermined priorities assigned to respective lots. In this way, a lot selecting process (step 138) is performed. When the next-processed lot is determined, the dispatch process is completed (step 139).
FIG. 21 is a flow chart illustrating details of the transfer execution process (step 134) in FIG. 19. A conventional transfer execution process is described in conjunction with FIG. 21.
According to the conventional transfer execution process, the process starts (step 140) to perform a transfer route determining step (step 141) for determining a transfer route of the next-processed lot designated in the dispatch process (step 132) based on the current position of the next-processed lot and positions of load ports 105a and 105b of processing apparatus 104 in which the next-processed lot is to be processed. Simultaneously, if the destination of the processed lot has been determined in the retrieve process (step 133), a step of determining a transfer route of the processed lot is performed based on the current position of the processed lot and the position of the destination, in the transfer route determining step (step 141).
Next, a transfer equipment control process (step 142) is performed for actually transporting the lot along the determined transfer route. In the transfer equipment control process (step 142), stocker 115 and transfer equipment such as intra-bay transfer apparatus 110 or inter-bay transfer apparatus 123 are controlled. In this way, the next-processed lot is sent to load port 105a or 105b of processing apparatus 104, or the processed lot is sent to stocker 115, for example. The transfer execution process is thereafter completed (step 143).
FIG. 22 shows a flow chart illustrating details of the retrieve process in FIG. 19. A conventional retrieve process (step 133) is described below in conjunction with FIG. 22.
The retrieve process starts (step 144) to perform a processing completion detecting process (step 145) for detecting completion of processing for all semiconductor wafers 101 in a lot including semiconductor wafer 101 being processed in processing apparatus 104 (completion of processing of the lot). When completion of the lot processing is detected, a destination selecting process (step 146) is conducted. In the destination selecting process (step 146), it is determined whether the processed lot is transported to stocker 115 or transported to load port 105a or 105b of another processing apparatus 104 in the same bay 172 in which the processed lot can undergo next processing. After the destination of the processed lot is determined, the process ends (step 147).
In the destination selecting process (step 146), it would be theoretically possible to convey the processed lot directly to load port 105a or 105b of another processing apparatus 104 instead of stocker 115. However, the processed lot can be conveyed directly to another processing apparatus 104 only under the conditions that another processing apparatus 104 is located in bay 172 in which the processed lot exists and that load port 105a or 105b in that another processing apparatus 104 is vacant.
The conventional lot transfer process has following problems.
In the dispatch process (step 132), vacancy of load ports 105a and 105b of processing apparatus 104 is detected (step 137) as shown in FIG. 20 and a next-processed lot is selected on the condition that load port 105a or 105b is vacant. Immediately after the dispatch process (step 132), the transfer execution process (step 134) is conducted to supply the next-processed lot to vacant load port 105a or 105b. Accordingly, in processing apparatus 104 shown in FIG. 17, for example, basically semiconductor wafer cassettes 102 are placed at respective load ports 105a and 105b and lots are placed in respective load lock chambers 106a and 106b all the time. In other words, two lots are loaded in processing apparatus 104. Suppose that one of the two lots which is placed in load lock chamber 106a has been processed. The processed lot is discharged from the processing apparatus so that load port 105a becomes vacant. Then, in the load port vacancy detecting process (step 137) of the dispatch process (step 132), the vacancy of load port 105a is detected. Immediately after this, a lot which can be processed in processing apparatus 104 is selected in the lot selecting process (step 138). The selected lot is quickly fed to load lock chamber 106a via load port 105a in the transfer execution process (step 134). At this time, however, the other lot which has been placed in load lock chamber 106b is being processed in processing apparatus 104. Therefore, during the processing of the other lot, the lot fed from load port 105a to load lock chamber 106a is on standby waiting for processing. In this standby state, even if another processing apparatus can start processing of the standby lot in load lock chamber 106a, no transfer process is done for sending the standby lot to that another processing apparatus. Consequently, the production term of the lot is prolonged.
A next-processed lot is selected on the condition that load port 105a or 105b is vacant and the next-processed lot is then fed to processing apparatus 104 as described above. Therefore, both of a lot being processed and a lot on standby exist in processing apparatus 104 all the time. In other words, there is always no vacancy in general since respective semiconductor wafer cassettes for those two lots are placed at respective load ports 105a and 105b of processing apparatus 104. Even if there is another lot having a higher priority than that of the standby lot which has already been loaded in processing apparatus 104, the processing of that another lot with a higher priority in processing apparatus 104 can be started only after processing of the standby lot is completed. Consequently, the lot having a higher priority cannot be processed in a short term.
Generically, there is always no vacancy in load ports 105a and 105b in the processing apparatus as described above. In one bay 172, if another processing apparatus can perform processing corresponding to the next process step for the lot which has been processed (processed lot) in processing apparatus 104 in that bay 172, the processed lot is not directly transported to that another processing apparatus and sent to stocker 115 instead in most of the cases since load ports of that another processing apparatus are not empty generally. In other words, a lot is transported from one process step to the next process step via stocker 115 in most instances, resulting in a prolonged production term of the lot.
If direct transfer of a lot is possible from a processing apparatus to another processing apparatus without passing the lot through stocker 115, the transfer process may be done once. On the other hand, the conventional lot transfer process requires that the transfer process is performed twice, one for transfering a processed lot to stocker 115 and one for transferring the lot to another processing apparatus which conducts processing in the next process step. Consequently, work load of intra-bay transfer apparatus 110 increases. The increased work load of intra-bay transfer apparatus 110 causes a processed lot or a next-processed lot to wait for being transported. This also results in a prolonged manufacturing term of the lot.
One object of the present invention is to provide a semiconductor device manufacturing apparatus and a control method thereof which can shorten manufacturing term of semiconductor devices without decrease in the amount of manufactured products.
According to one aspect of the invention, a control method of a semiconductor device manufacturing apparatus is provided which includes a plurality of processing apparatuses which successively draw out and process a plurality of semiconductor wafers constituting a process lot and which include a standby port where a lot is on standby to be processed next (next-processed lot) after processing of the process lot. The manufacturing apparatus further includes a stocker holding a lot to be transported to the standby port. The control method includes a prediction step, a time setting step, a lot selecting step and a transfer step. In the prediction step, it is predicted when processing starts for the last semiconductor wafer among semiconductor wafers which were on standby in the processing apparatus and consequently there is no standby wafer left in the processing apparatus. In the time setting step, using the time when there is no standby wafer left in the processing apparatus, transfer starting time is set for starting transfer of a next-processed lot to the standby port in order to enable successive processing of following semiconductor wafers to start after the last semiconductor wafer is processed. In the lot selecting step, a next-processed lot is selected. In the transfer step, the next-processed lot is transferred to the processing apparatus at or after the transfer starting time.
In this way, the time at which there is no standby wafer left in the processing apparatus is predicted to transfer the next-processed lot to the processing apparatus timely such that successive processing in the processing apparatus is possible. Consequently, the next-processed lot is never fed to the standby port when there remain many unprocessed wafers in a lot being processed. Thus, the next-processed lot is never put on standby at the standby port for a long period of time. In the time period in which the next-processed lot should be on standby at the standby port according to the conventional control method, suppose that another processing apparatus can process the next-processed lot. According to the present invention, the next-processed lot can be transported properly to that another processing apparatus and thus semiconductor wafers can be processed more quickly. As a result, the manufacturing term of semiconductor devices can be shortened without decrease in the amount of manufactured products.
According to the present invention, the next-processed lot would never remain in standby state for a long time at the standby port. Therefore, delay can be avoided in processing for a lot having a high processing priority, which delay is caused by the long-period presence of the next-processed lot at the standby port.
According to the one aspect of the invention, in the lot selecting step of the control method of the semiconductor device manufacturing apparatus, preferably the next-processed lot is selected at or after the transfer starting time.
In this case, the next-processed lot is selected at the time as near as possible to the starting time for processing the next-processed lot in the processing apparatus. The time from selection of a next-processed lot to processing of the next-processed lot can be made shorter than that in the conventional method. Further, the selection of the next-processed lot is made at the time as close as possible to the starting time of the processing of the next-processed lot in the processing apparatus. Then, a lot having a high priority for being processed, which is actually selectable as a next-processed lot at the processing starting time in the processing apparatus but which cannot be selected in the conventional method due to the time limitation, can be selected as a next-processed lot. (Such a high-priority lot is not selected as a next-processed lot in the processing apparatus and put on standby for being processed in another processing apparatus in the conventional method.) The high-priority lot can accordingly be processed in the processing apparatus earlier compared with the conventional method. Reduction of manufacturing term of the high-priority lot is thus ensured.
According to the one aspect of the invention, the control method of the semiconductor device manufacturing apparatus preferably includes the step of predicting the time required for the transfer step (the step of predicting transfer time). The predicted transfer time is preferably used in the time setting step to determine the transfer starting time.
Precise prediction of the transfer time would enable the transfer starting time to be set more accurately. If the transfer starting time is set less accurately, for example, if the determined transfer starting time is too earlier than the optimum time, the next-processed lot should be on standby at the standby port for a long period of time. On the contrary, if the determined transfer starting time is later than the optimum time, the next-processed lot is not in time for being processed in the processing apparatus resulting in the period in which wafers to be processed in the processing apparatus are waited for. If the precision of setting the transfer starting time can be improved, this problem can be avoided. The manufacturing term of the semiconductor device is thus surely shortened.
According to the one aspect of the invention, the control method of the semiconductor device manufacturing apparatus, preferably the transfer time is predicted based on the actual transfer time.
According to the one aspect of the invention, in the control method of the semiconductor device manufacturing apparatus, preferably the step of predicting transfer time includes the steps of measuring the actual transfer time and predicting the transfer time using the actual transfer time.
In this way, the transfer starting time can be determined more precisely by predicting the transfer time based on the actual transfer time.
According to the one aspect of the invention, the control method of the semiconductor device manufacturing apparatus preferably includes the step of predicting when processing is completed for another process lot including a semiconductor wafer being processed in another processing apparatus. In the lot selecting step, the predicted completion time is used to select a next-processed lot, which can be transferred to the standby port, from that another process lot and any lot held in the stocker. As a result, after the last semiconductor wafer has been processed, processing of the next semiconductor wafer can be started successively.
In this case, the next-processed lot can be selected from the group consisting of the another process lot being processed in another processing apparatus and any lot stored in the stocker, so that the another lot being processed in another processing apparatus can be selected as a next-processed lot. Then, the next-processed lot can be transported directly from that another processing apparatus to the processing apparatus. The step in the conventional method of transferring and storing a processed lot into the stocker is thus unnecessary. Shortening of the manufacturing term of the semiconductor device is accordingly achieved.
The number of required transfer steps can be reduced by one compared with the conventional method in which the processed lot is stored in the stocker and then conveyed to the processing apparatus. As a result, reduction is possible of the working load of the transfer equipment which transfers lots between the stocker and the processing apparatus. The problem that standby wafers occur in the processing apparatus due to the high working load of the transfer apparatus is thus prevented. Extension of the manufacturing term of the semiconductor device due to such occurrence of the standby wafers can be avoided.
According to another aspect of the invention, a semiconductor device manufacturing apparatus includes a plurality of processing apparatuses which successively draw out and process a plurality of semiconductor wafers constituting a process lot and which include a standby port where a lot is on standby to be processed next (next-processed lot) after processing of the process lot. The manufacturing apparatus includes a stocker holding a lot to be transported to the standby port. The semiconductor device manufacturing apparatus further includes prediction means, time setting means, lot selecting means and transfer means. The prediction means predicts when processing starts for the last semiconductor wafer among semiconductor wafers which were on standby in the processing apparatus and consequently there is no standby wafer left in the processing apparatus. The time setting means uses the time when there is no standby wafer left in the processing apparatus to set transfer starting time for starting transfer of a next-processed lot to the standby port in order to enable successive processing of following semiconductor wafers to start after the last semiconductor wafer is processed. The lot selecting means selects a next-processed lot. The transfer means transfers the next-processed lot to the processing apparatus at or after the transfer starting time.
In this way, the time when there remains no standby wafer in the processing apparatus is predicted to determine the transfer starting time based on that time and then transfer the next-processed lot to the processing apparatus at or after the transfer starting time at the standby port. Consequently, the next-processed lot is never fed to the standby port when there remain many unprocessed wafers in a lot being processed. Thus, the next-processed lot is never put on standby for a long period of time at the standby port. As a result, the manufacturing term of semiconductor devices can be shortened.
The next-processed lot would never remain in standby state for a long time at the standby port. Therefore, delay can be avoided in processing for a lot having a high processing priority, which delay is caused by the long-period presence of the next-processed lot at the standby port.
According to the another aspect of the invention, preferably the lot selecting means never selects the next-processed lot before the transfer starting time.
In this case, the next-processed lot is selected at the time as close as possible to the starting time for processing the next-processed lot in the processing apparatus. If there is a lot having a higher processing priority, this lot with a high priority can be selected as a lot to be processed next in the processing apparatus, and the lot can thus be processed quickly.
According to the another aspect of the invention, preferably the semiconductor device manufacturing apparatus includes means for predicting the time required for transferring the next-processed lot to the processing apparatus. The predicted transfer time is preferably used by the time setting means to determine the transfer starting time.
Precise prediction of the transfer time would enable the transfer starting time to be set more accurately. If the transfer starting time is away from the optimum time, the next-processed lot should wait for being processed at the standby port for an increased time or there is a wasteful time for waiting for arrival of the lot in the processing apparatus. By avoiding such wasteful time period, the manufacturing term of semiconductor devices can surely be shortened.
According to the another aspect of the invention, the transfer time predicting means preferably uses an actual time for transferring the next-processed lot to the processing apparatus to predict the transfer time.
According to the another aspect of the invention, the transfer time predicting means preferably includes means for measuring the actual transfer time for transferring the next-processed lot by the transfer means to the processing apparatus, and means for predicting the transfer time using the actual transfer time.
In this way, the transfer starting time can be determined more precisely by predicting the transfer time based on the actual transfer time.
According to the another aspect of the invention, the semiconductor device manufacturing apparatus preferably includes means for predicting when processing is completed for another process lot including a semiconductor wafer being processed in another processing apparatus. The lot selecting means uses the predicted completion time to select a next-processed lot, which can be transferred to the standby port, from that another process lot and any lot held in the stocker. As a result, after the last semiconductor wafer has been processed, processing of the next semiconductor wafer can be started successively.
In this case, the next-processed lot can be selected from the group consisting of the another process lot being processed in another processing apparatus and any lot stored in the stocker, so that the another lot being processed in another processing apparatus can be selected as a next-processed lot. Then, the next-processed lot can be transported directly from that another processing apparatus to the processing apparatus. The step of storing a processed lot in the stocker is thus unnecessary. Shortening of the manufacturing term of semiconductor devices is accordingly possible.
The number of required transfer steps can be reduced by one compared with the conventional method. As a result, reduction is possible of the working load of the transfer equipment which transfers lots between the stocker and the processing apparatus. Then, the wasteful time for waiting for a lot in the processing apparatus due to the high working load of the transfer equipment can be avoided.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.